The present invention relates to an on die thermal sensor (ODTS) having an analog-to-digital converter (ADC) in a semiconductor memory device, and more particularly, to an ADC that performs a converting operation differently during and after an initial tracking period, and an ODTS for use in a semiconductor memory device having the same.
An analog-to-digital conversion is an electronic process of converting an analog signal into a digital signal without changing inherent contents of the analog signal.
An analog-to-digital converter (ADC) is an electronic circuit that converts a continuous analog signal into a discrete digital signal.
The reason for the analog-to-digital conversion is because the digital signals are clear and regular compared with the analog signals, and an electronic circuit which discriminates signals from disordered noise can be designed so easily that the signals can be transferred more efficiently.
Meanwhile, as the integration level and operating speed of a semiconductor memory device increases, a large amount of heat is generated from the semiconductor memory device. Since the generated heat increases internal temperature of the semiconductor memory device, the semiconductor memory device may be abnormally operated or damaged. Therefore, there is a need for a device for correctly detecting the temperature of the semiconductor memory device and outputting information about the detected temperature.
An ODTS is a device that measures the internal temperature of the semiconductor memory device and outputs information about the measured temperature in digital values.
Meanwhile, in order to prevent data loss, a dynamic random access memory (DRAM) reads data from a DRAM cell before the data is lost and recharges the DRAM cell according to the read data.
The operation of recharging the DRAM cell is referred to as a refresh operation. The data can be retained in the DRAM cell by repeating refresh operation periodically.
The refresh operation of the DRAM dissipates a refresh power. The reduction of power consumption is an important and critical issue to a low-power battery operated system.
One of many attempts to reduce power consumption in the refresh operation is to change a refresh period according to temperature. As the temperature becomes lower, the data retention time in the DRAM becomes longer. Therefore, the power consumption can be reduced by dividing a temperature range into a plurality of sub-ranges and relatively reducing a refresh clock frequency at a low temperature range. Therefore, there is a need for a device that can correctly detect the internal temperature of the DRAM and output information about the detected temperature.
However, the ODTS measures the internal temperature of the semiconductor device using the fact that the change in a base-emitter voltage (VBE) of a bipolar junction transistor (BJT) is about −1.8 mV/° C.
That is, the measurement of the internal temperature of the semiconductor memory device is to output temperature voltage having a predetermined voltage level according to the internal temperature of the semiconductor memory device. The temperature voltage means a voltage obtained by amplifying the base-emitter voltage (VBE) of the BJT to a predetermined level.
However, since other components of the semiconductor memory device, e.g., a refresh controller, requires digital temperature information, an ADC is necessary which can convert an analog value of the base-emitter voltage (VBE) of the BJT into a digital value.
Among various kinds of ADCs, a tracking ADC is most widely used in the semiconductor memory device. The tracking ADC tracks a level of an input voltage and determines a corresponding digital code.
FIG. 1 is a block diagram of a conventional tracking ADC 1.
Referring to FIG. 1, the conventional tracking ADC 1 includes a comparing unit 12 and a voltage level determining unit 13. The comparing unit 12 compares a level of a temperature voltage VTEMP with a level of a tracking voltage DACOUT and changes a value of a digital code DIGITAL_CODE according to the result of comparison. The voltage level determining unit 13 determines the level of the tracking voltage DACOUT in response to a test code TEST_CODE during a test mode operation, but the digital code DIGITAL_CODE is outputted from the comparing unit 12 during a normal mode operation.
In addition, the conventional tracking ADC 1 further includes a clock oscillating unit 14. The clock oscillating unit 14 controls an on/off operation of the comparing unit 12 by oscillating a clock signal CLK input to the comparing unit 12 in response to a converting control signal ADC_ON.
The comparing unit 12 includes a comparator 121 and an up/down counter 122. The comparator 121 compares the level of the temperature voltage VTEMP with the level of the tracking voltage DACOUT and determines logic levels of an increment signal INC and a decrement signal DEC according to the result of comparison. The up/down counter 122 changes the value of the digital code DIGITAL_CODE according to the increment signal INC and the decrement signal DEC.
The comparing unit 12 further includes a low pass filter (LPF) 123 for low-pass-filtering the increment signal INC and the decrement signal DEC.
When the level of the temperature voltage VTEMP is lower than that of the tracking voltage DACOUT, the comparator 121 activates the increment signal INC and deactivates the decrement signal DEC.
On the other hand, when the level of the temperature voltage VTEMP is higher than that of the tracking voltage DACOUT, the comparator 121 deactivates the increment signal INC and activates the decrement signal DEC.
The up/down counter 122 resets the digital code DIGITAL_CODE to a set value in response to the converting control signal ADC_ON.
The LPF 123 transfers the increment signal INC and the decrement signal DEC to the up/down counter 122 when they have correct information. On the contrary, the LPF 123 does not transfer the increment signal INC and the decrement signal DEC to the up/down counter 122 when they do not have correct information due to the erroneous operation of the comparator 121.
Upon the filtering operation, the increment signal INC and the decrement signal DEC are not directly transferred to the up/down counter 122 even though the logic levels of the increment signal INC and the decrement signal DEC are determined at the first clock and are inputted to the LPF 123. Instead, whether to transfer the increment signal INC and the decrement signal DEC is determined after detecting the logic levels of the increment signal INC and the decrement signal DEC at the second and third clocks.
That is, when the comparator 121 operates normally, the logic levels of the successively-inputted increment signal INC and decrement signal DEC does not change abruptly. Therefore, whether the comparator 121 operates normally is determined by detecting the logic levels of the increment signal INC or the decrement signal DEC that is successively inputted three times.
The voltage level determining unit 13 includes a multiplexer 131 and a digital-to-analog converter (DAC) 132. The multiplexer 131 selects one of the digital code DIGITAL_CODE and the test code TEST_CODE in response to a test mode operation signal TEST_MODE. The DAC 132 determines the level of the tracking voltage DACOUT in response to the digital code DIGITAL_CODE or the test code TEST_CODE outputted from the multiplexer 131.
In addition, the voltage level determining unit 13 includes a decoder 133 for decoding the output signal of the multiplexer 131 to output a decoding signal group SW<0:N>, N being a positive integer, so that occurrence of undesired glitch in the DAC 132 can be prevented.
An upper limit voltage VULIMIT input to the DAC 132 is a voltage at which the level of the tracking voltage DACOUT can be determined to be maximum. A lower limit voltage VLLIMIT input to the DAC 132 is a voltage at which the level of the tracking voltage DACOUT can be determined to be minimum. The upper limit voltage VULIMIT and the lower limit voltage VLLIMIT are defined by the user.
At this point, the multiplexer 131 selects one of the digital code DIGITAL_CODE and the test code TEST_CODE in order to test the operation of the tracking ADC 1 according to the user's selection.
Since the multiplexer 131 and the decoder 133 are provided for supplementary operation of the tracking ADC 1, the basic operation of the tracking ADC 1 can be performed without them.
When the tracking ADC 1 operates in response to the activated counter control signal ADC_ON, the clock oscillating unit 14 controls the operations of the comparator 121, the LPF 123, and the up/down counter 122 by oscillating the clock signal CLK in response to the converting control signal ADC_ON.
The reason why the clock oscillating unit 14 and the clock signal CLK are necessary for the tracking ADC 1 is as follows.
An object of the tracking ADC 1 is to find the digital code DIGITAL_CODE corresponding to the temperature voltage VTEMP. Assuming that the level of the inputted temperature voltage VTEMP is fixed, the level of the tracking voltage DACOUT is changed until the level of the temperature voltage VTEMP becomes equal to that of the tracking voltage DACOUT.
The level of the tracking voltage DACOUT can be changed by varying the value of the digital code DIGITAL_CODE. Since the tracking voltage DACOUT having the level equal to that of the temperature voltage VTEMP cannot be found by varying the unit of the digital code DIGITAL_CODE only one time, the operation of varying the value of the digital code DIGITAL_CODE must be performed several times.
That is, in order to repeat the operation of varying the value of the digital code DIGITAL_CODE several times, the comparator 121, the LPF 123, and the up/down counter 122 are turned on/off several times using the clock signal CLK that continuously toggles while the converting control signal ADC_ON is in the active state.
A plurality of delay circuits DLY1, DLY2 and DLY3 are provided among the comparator 121, the LPF 123, and the up/down counter 122 in order to define their operation order in transferring the clock signal CLK.
That is, if the LPF 123 and the up/down counter 122 operate while the comparator 121 does not finish its operation, the tracking ADC 1 cannot operate normally. Therefore, the plurality of delay circuits DLY1, DLY2 and DLY3 are provided for transferring the clock signal CLK at constant time intervals according to the operation order of the respective units.
In addition, delay time of the plurality of delay circuits DLY1, DLY2 and DLY3 may be different and is previously determined by the user or designer.
Whenever the clock signal CLK is toggled, the operation of varying the value of the digital code DIGITAL_CODE is performed one time. Thus, the final output of the clock signal CLK can be used as an update signal indicating that the digital code value is changed.
The tracking ADC can be classified into a sequential access ADC and a successive approximation register (SAR) ADC, depending on the converting methods.
The sequential access ADC finds the digital code corresponding to the inputted analog value by increasing or decreasing the digital code, which is outputted when the clock signal CLK is toggled one time, from the least significant bit (LSB) by 1.
The SAR ADC finds the digital code corresponding to the inputted analog value by increasing or decreasing the digital code DIGITAL_CODE, which is outputted when the clock signal CLK is toggled one time, from the most significant bit (MSB) by 1.
FIG. 2A is a flowchart showing a converting operation of the SAR ADC.
Referring to FIG. 2A, the desired digital code value is found by increasing or decreasing the digital code DIGITAL_CODE from the MSB by 1.
FIG. 2B is a timing diagram of signals used in an ODTS using the sequential access ADC.
Referring to FIG. 2B, the operation of the ODTS using the sequential access ADC is as follows.
First, a temperature detection control signal BGR_ON is activated in response to the toggling of an enable signal ENABLE, as indicated by a reference number “1”.
Second, the ODTS detects the temperature in response to the activated temperature detection control signal BGR_ON. Then, the levels of the upper limit voltage VULIMIT and the lower limit voltage VLLIMIT containing the temperature voltage VTEMP are initialized, as indicated by a reference numeral “2”. The temperature voltage means a voltage output according to the detected temperature. At this point, the time during which the temperature detection control signal BGR_ON is activated and maintained is set by the user.
Third, a converting control signal ADC_ON is activated at the same time when an initialization of the temperature detection voltage is finished, as indicated by a reference numeral “3”.
Fourth, the ODTS performs the counting operation of the sequential access ADC in response to the activated converting control signal ADC_ON, as indicated by a reference numeral “4”.
At this point, a time during which the converting control signal ADC_ON is activated and maintained is set by the user.
In the converting operation of the sequential access ADC in the ODTS, the tracking voltage DACOUT has a small unit variation width in order to have the same value (a value within an error range) as the level of the temperature voltage VTEMP.
That is, in the converting operation of the sequential access ADC, the ODTS operates while maintaining the level of the tracking voltage DACOUT with a small unit variation width for a relatively long time and then finds a value equal to the level of the temperature voltage VTEMP, i.e., a value within an error range.
The sequential access ADC is implemented with a simple circuit, but has the following problems.
First, because the digital code value is increased or decreased from the LSB by 1 when the clock signal CLK is toggled one time, it takes a relatively long time to find the digital code DIGITAL_CODE corresponding to the level of the temperature voltage VTEMP.
Second, when a plurality of temperature voltages are inputted with different voltage levels, time taken to find the digital code value corresponding to the voltage level varies depending on the respective temperature voltage
That is, time taken to convert the digital code DIGITAL_CODE varies depending on the level of the plurality of temperature voltages.
When a plurality of signals have different levels of the inputted temperature voltages, the time to find the digital code values corresponding to the levels of the temperature voltage VTEMP changes depending on the levels of the temperature voltage VTEMP.
FIG. 2C is a timing diagram of signals used in the ODTS using the SAR ADC.
Referring to FIG. 2C, the operation of the ODTS using the SAR ADC is as follows.
First, a temperature detection control signal BGR_ON is activated in response to the toggling of an enable signal ENABLE, as indicated by a reference number “1”.
Second, the ODTS detects the temperature in response to the activated temperature detection control signal BGR_ON. Then, the levels of the upper limit voltage VULIMIT and the lower limit voltage VLLIMIT containing the temperature voltage VTEMP are initialized, as indicated by a reference numeral “2”. The temperature voltage is a voltage output according to the detected temperature.
At this point, the time during which the temperature detection control signal BGR_ON is activated and maintained is set by the user.
Third, a converting control signal ADC_ON is activated at the same time when the initialization of temperature detection voltage is finished, as indicated by a reference numeral “3”.
Fourth, the ODTS performs the counting operation of the SAR ADC in response to the activated converting control signal ADC_ON, as indicated by a reference numeral “4”.
At this point, the time during which the converting control signal ADC_ON is activated and maintained is set by the user.
In the converting operation of the SAR ADC in the ODTS, the tracking voltage DACOUT has a large unit variation width in order to have the same value (a value within an error range) as the level of the temperature voltage VTEMP.
That is, in the converting operation of the SAR ADC, the ODTS operates while maintaining the level of the tracking voltage DACOUT with a large unit variation width for a relatively short time and then finds a value equal to the level of the temperature voltage VTEMP, i.e., a value within an error range.
Like the sequential access ADC, the SAR ADC is implemented with a simple circuit and it takes a short time to find the digital code corresponding to the level of the temperature voltage VTEMP. However, the SAR ADC has the following drawbacks that do not occur in the sequential access ADC.
First, when the level of the inputted temperature voltage VTEMP changes during the converting operation, the accuracy of the found digital code DIGITAL_CODE is not reliable.
That is, an operation of locking the inputted temperature voltage VTEMP using sample/hold is necessary during a full-tracking operation of determining all bit values in order from the MSB to the LSB.
Second, even after the digital code corresponding to the level of the temperature voltage VTEMP is found through the full-tracking operation during the initial converting operation, as indicated by a reference symbol “A”, the full-tracking operation must be again performed so as to find a correct digital code DIGITAL_CODE if the level of the temperature voltage VTEMP is changed, as indicated by reference symbols “B”, “C” and “D”.
That is, the full-tracking operation of increasing or decreasing the digital code from the MSB to the LSB by 1 must be performed even though the level of the temperature voltage VTEMP is slightly changed during the converting operation after the initial converting operation.